As FPGA prices continue to fall, broad availability of IP such as low-cost processors, DSP cores, and peripherals will be instrumental in allowing these devices to become system platforms for a widening range of applications. Implementing an entire embedded system within a programmable device is an attractive proposition for many reasons, but integrating the required hard and soft design elements remains a formidable challenge.

Technical barriers

The technical barriers to implementing IP in FPGAs are considerable. This is because ‘soft’ components are rarely delivered to designers in ‘ready-to-use’ condition for their specific application. The HDL-coded description of the core must be integrated with other elements of the design and verified as part of a complex system. Although up to 40% of hardware designers are utilizing FPGAs in at least some of their products, only a small percentage of these engineers have either the expertise or tools to perform high-level VHDL or Verilog design flows. These facts often relegate the FPGA into a supporting role for a dedicated processor or microcontroller when it could potentially deliver the entire system.

Significant benefits

The benefits of implementing a system on a programmable platform are significant. It allows designers to shrink the product footprint while exploiting reconfigurable hardware. There is also the potential to provide a platform for embedded software development and debugging much earlier in the design cycle while delaying the need to freeze the hardware design.

" The technical barriers to implementing IP in FPGAs are considerable ...soft components are rarely delivered to designers in �ready-to-use� condition for their specific application. "

Beyond the technical issues associated with implementing IP-based designs, there are the complex licensing issues encountered when obtaining IP or delivering it to customers. Because IP has traditionally been delivered to the designer as source code, the security of that source is of paramount importance to its owner. This requires a complex legal framework to protect the IP and to provide licensing schemas for its distribution to end-customers. So significant is this barrier to implementing system-level designs, that it has spawned a lively open-source movement for hardware IP. However, the potential misfit between the objectives of ‘free’ IP cores advocates and the needs of developers of commercial applications for that IP creates its own set of issues.

FPGA vendors have recognized the importance of IP and have responded by providing their own sources and licensing. However, these cores are targeted only for the vendor’s own platforms and have a proprietary architecture, limiting their application. From a usability perspective, these proprietary approaches are bound by the FPGA vendor tools’ lack of integration with the balance of the design flow that happens ‘outside the chip’.

Portability

Before widespread exploitation of the full potential of programmable, ‘system-capable’ platforms can be achieved, the implementation and licensing issues that continue to restrict IP access must be resolved. The solution must preserve design portability and be built upon standard rather than proprietary processor architectures.

Altium has introduced a new delivery method for IP. We have taken the HDL source for soft cores (both processors and peripheral components) and synthesized these into ready-to-use components. These soft components are containers of pre-synthesized code that are ready for fitting into an FPGA without further modification by the designer. By linking these pre-synthesized components to schematic symbols, the designer can work graphically in Altium Designer with blocks of IP code without having to be exposed to the complexities of the underlying HDL.

These pre-synthesized/pre-verified components are treated as black boxes during system synthesis, which provides the additional benefit of speeding the re-processing of the design each time it is downloaded into the FPGA. This gives the designer the freedom to iterate the design at will without the overhead of tedious synthesis and verification cycles that extend down below the component level.

Starting point

Of course, the key to the ultimate value of this approach will be the number of potential design applications this new methodology supports.

We have already developed pre-synthesised components for a number of standard 8-, and 32-bit microprocessors and microcontrollers. These will provide a starting point for our customers to explore system implementations utilizing the low-cost FPGAs that are currently on the market. As the price of larger FPGAs falls, we will continue to add increasingly sophisticated models to the device libraries, without the need to license them separately or pay royalties for each use of the IP.

Since the Altium IP delivery platform provides a powerful and secure model for both distributing and implementing IP, we anticipate a lively and growing mix of both commercial and open-source IP to support the wide range of products being designed by our customers.